 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| AN180 Application Note USING A PLL TO GENERATE CLOCKS FOR DIGITAL AUDIO Note: Cirrus Logic assumes no responsibility for the attached information which is provided "AS IS" without warranty of any kind (expressed or implied). P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com Copyright (c) Cirrus Logic, Inc. 2000 (All Rights Reserved) SEP `00 AN180REV2 1 AN180 TABLE OF CONTENTS 1. INTRODUCTION ....................................................................................................................... 3 2. BACKGROUND ........................................................................................................................ 3 3. CIRCUIT DESCRIPTION .......................................................................................................... 3 LIST OF TABLES Table 1. List of Audio Sample Rates and Corresponding Frequency Select Bits ........................... 5 LIST OF FIGURES Figure 1. Typical PLL Circuit ........................................................................................................... 4 Figure 2. EP7209/12/7312 ICS548-02 Interface ............................................................................. 4 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 AN180REV2 AN180 1. INTRODUCTION This application note describes how to use a lowcost PLL (Phase Lock Loop) circuit to generate sample frequencies required for high quality digital audio for use with MP3. programmable, then multiple frequency outputs are generated. 3. CIRCUIT DESCRIPTION Refer to Figure 2 while reading this section. The circuit is based upon the Integrated Circuit Systems ICS548-02, a low-cost, low-jitter, highperformance clock synthesizer designed to produce audio sampling rates for MP3 and other digital audio systems. Using analog/digital Phase-Locked Loop (PLL) techniques, the device uses an inexpensive 14.7456 MHz or 3.6864 MHz crystal input to produce 256x all of the popular audio sampling frequencies. With a separate 3.6864 MHz input, the chip provides a clock output, allowing it to drive the MCLK input on the CS43L41 directly. Alternatively, the MOSCOUT oscillator drive output of the EP7209/12/7312 can provide the clock to the ICS548-02. This approach may be the preferred method to use since the EP7209/12/7312 manages the power consumption by going into a Standby mode when not in use. This mode effectively disables the 3.6864 MHz oscillator that reduces overall system power consumption. Using the external 14.7456 MHz oscillator, the PLL will generate MCLK for all sampling frequencies except 8 KHz. The ISC548-02 uses 4 digital inputs to select the frequency (S0, S1, S2, and S3). The control inputs can be connected directly to four GPIO output pins of the EP72xx and adjusted under software control. Table 1 lists the frequencies generated by the ICS548-02 PLL circuit as a function of the four input select pins. Notice that S3 is always a one. This pin could be wired to Vdd freeing up an extra 72xx/7312 GPIO pin. 2. BACKGROUND Cirrus Logic EPD-7209/12/7312 ARM(R)-based microcontrollers are capable of decoding MP3 digital audio in real time. The decoded bit stream is sent to a Crystal CS43L41 DAC using a high-speed Digital Audio Interface (DAI). The DAC requires an MCLK clock signal that is 256 times the desired sample rate. A typical sample rate for MP3 digital audio is 44.1 kHz, but other frequencies are used as well, including 8-, 16-, 22.05-, 24-, 32-, and 48 kHz. A PLL clocking scheme is capable of producing these clocks with little or no error. Although it is possible to use the DSP capabilities of the ARM processor to do software sample rate conversion (SRC), a hardware approach is much simpler and reduces the number of MIPS (and thereby the power consumption) required of the processor. (Software SRC is supported by Cirrus Logic's MP3 player software.) A brute-force (and potentially more expensive) method of providing multiple clocks is to switch between separate crystal oscillators. A better choice is to take advantage of PLL technology to synthesize the desired frequencies using one crystal source. A PLL can be used to multiply a reference frequency by placing a divider circuit in the feedback loop from the VCO (voltage controlled oscillator) output to the phase comparator input as shown in Figure 1. If the divider circuit is AN180REV2 3 AN180 CLKREF Reference Clock Phase Comparator Loop Filter Programmable Divide by N Counter VCO (Voltage Control Oscillator) S[3..0] FOUT=CLKREF*N Figure 1. Typical PLL Circuit 3.6864 MHz MOSCOUT 0.01 F X1 10K GPIO[0..3] S[0:3] CLK MCLK CS43L41 DAC EP7209 SYNC SCLK SDTX IC548-02 Figure 2. EP7209/12/7312 ICS548-02 Interface 4 AN180REV2 AN180 Desired Sampling Rate (Kilo-Hertz) 8 16 22.05 24 32 44.1 48 Output Clock 256 x SR (Mega-Hertz) 2.048 4.096 5.6448 6.144 8.192 11.2896 12.288 Frequency Select Pins S3 1 1 1 1 1 1 1 S2 1 0 0 0 1 1 1 S1 1 0 0 1 0 0 1 S0 1 0 1 0 0 1 0 Table 1. List of Audio Sample Rates and Corresponding Frequency Select Bits NOTE: Actual values are 256 times the desired sample rate. Reference clock for this table is 3.6864 MHz. AN180REV2 5 |
Price & Availability of AN180-2
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |